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Main text(s) Main text(s) English Protection of Layout Designs (Topographies) of Integrated Circuits Regulations - Chapter 17.13.01 (2020 Revised Edition)      

Additional Text(s) WTO Notifications Coversheet (3 text(s)) WTO Notifications Coversheet (3 text(s)) French Règlement sur la protection des schémas de configuration (topographies) des circuits intégrés (chapitre 17.13.01, révisée de 2020) Spanish Reglamento de Protección de Esquemas de Trazado (Topografías) de Circuitos Integrados (Capítulo 17.13.01, Edición Revisada 2020) English Protection of Layout Designs (Topographies) of Integrated Circuits Regulations - Chapter 17.13.01 (2020 Revised Edition)

Legislation Implements (1 text(s)) Implements (1 text(s))

• Protection of Layout Designs (Topography) of Integrated Circuits Act 2002 (Act No. 18 of 2002, 2020 Revised Edition) (TO026)

WTO Document Reference

IP/N/1/TON/3

IP/N/1/TON/L/2