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Protection of Layout Designs (Topographies) of Integrated Circuits Regulations - Chapter 17.13.01 (2020 Revised Edition), Tonga

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Details Details Year of Version 2020 Dates Entry into force: December 8, 2009 Type of Text Implementing Rules/Regulations Subject Matter Layout Designs of Integrated Circuits Subject Matter (secondary) IP Regulatory Body

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Main Text(s) Related Text(s)
Main text(s) Main text(s) English Protection of Layout Designs (Topographies) of Integrated Circuits Regulations - Chapter 17.13.01 (2020 Revised Edition)      
 
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Additional Text(s) WTO Notifications Coversheet (3 text(s)) WTO Notifications Coversheet (3 text(s)) French Règlement sur la protection des schémas de configuration (topographies) des circuits intégrés (chapitre 17.13.01, révisée de 2020) Spanish Reglamento de Protección de Esquemas de Trazado (Topografías) de Circuitos Integrados (Capítulo 17.13.01, Edición Revisada 2020) English Protection of Layout Designs (Topographies) of Integrated Circuits Regulations - Chapter 17.13.01 (2020 Revised Edition)
 
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Legislation Implements (1 text(s)) Implements (1 text(s)) WTO Document Reference
IP/N/1/TON/3
IP/N/1/TON/L/2
No data available.

WIPO Lex No. TO030